Once the A/D conversion is complete, it must be transferred from the board to the system memory where the application software can use it. There are two main methods for transferring data:
Foreground means that the application software directly reads the data from the board. This is typical for occasional sampling, where the rate of A/D sampling is very low (for example measuring a temperature once a second) and the sampling is done on demand by the application.
Background means that the data is transferred automatically without the application having to directly control it. This method is used for high-speed sampling (for example digitizing a strain gage signal at 50KHz).
There are two main types of background data transfer: Interrupts and DMA (direct memory access).
In interrupt operation, the board generates a hardware interrupt request, causing a software interrupt routine to execute. The interrupt routine reads out the data from the board and stores it in memory. The interrupt routine is typically provided in the driver software for the board. An interrupt routine requires a significant amount of software overhead beyond simply reading the data from the board. Therefore advanced A/D boards include a FIFO (first-in first-out memory) feature to reduce the interrupt rate. Because data is read out from the board in large chunks (for example 256 samples at a time), the interrupt rate can be slowed down significantly, dramatically improving overall application performance:
In DMA operation, there is no software at all. The board initiates a DMA request, and the processor responds with an acknowledge cycle, transferring the data from the board directly to memory in a single bus cycle. This transfer occurs in between software instructions, so from the software's perspective it happens invisibly. However there is some time delay incurred since the transfer cycle is being inserted between software instruction cycles, slowing down the rate of software execution. The amount of the slowdown depends entirely on the rate of DMA cycles.
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