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Products   >   I/O Expansion Modules   >   Digital I/O Modules   >   GPIO-MM Digital I/O Module
FPGA-based digital I/O module with reprogrammable feature sets: 64 digital I/O + 10 16-bit counter/timers , 96 digital I/O, and custom designs
RAM-based field-reprogrammable FPGA with 200K gates
3 I/O connectors for a total of 100 I/O pins
2 programmable interrupts
8 diagnostic LEDs
40 MHz on-board clock to drive digital logic
-40C to +85C operation
FREE Universal Driver software included
Customers who use this product also use:
50-pin Data Acquisition Cable

This product can be customized and ruggedized. Click here for more information.
See GPIO-MM Digital I/O Module Technical Resources
Request Product information
Request Technical Support
GPIO-MM Datasheet
(.pdf, 331.4 kb)
GPIO-MM-11 User Manual
(.pdf, 463.5 kb)
Universal Driver 6.02 Release Notes
(.pdf, 141.3 kb)
GPIO-MM Personality Guide v1.01
(.pdf, 239.5 kb)
GPIO-MM FPGA Pinout Guide
(.pdf, 331.4 kb)
GMM to GPIO-MM Transition Guide
(.pdf, 49.5 kb)
Universal Driver Software
Universal Driver 6.02 for DOS
(.zip, 176.5 kb)
Universal Driver 6.02 for Windows CE
(.zip, 106.7 kb)
Universal Driver 6.02 for Windows XP
(.zip, 331.8 kb)
Universal Driver 6.02 for Linux
(.bz2, 148.7 kb)

GPIO-MM Digital I/O Module

Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module

GPIO-MM Digital I/O Module
click for a larger image
Block Diagram
I/O Connectors
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GPIO-MM is a PC/104 digital I/O module based on an FPGA, allowing multiple feature sets to be implemented on the same hardware platform. The FPGA is a Xilinx Spartan 2 RAM-based device with 200K gates (XC2S200). An on-board configuraton flash memory device stores the FPGA code for automatic loading on power-up, and new code can be downloaded using a JTAG cable connected to a PC. Several standard off the shelf personalities are available, and custom ones can be developed either by users with Xilinx tools or by Diamond as a customization service.

The right side I/O connector includes ESD protection circuitry for increased reliability, while the left side I/O connector offers high-drive logic buffers for increased load compatibility, along with jumper-configured pull-up / pull-down resistors. All digital I/O pins are set to input on power-up to avoid conflicts with external circuitry.

Hardware configuration options include jumper-selectable base address and DMA level, plus a 10-position jumper lock for user-definable field configurability when used with custom designs. A 256-byte EEPROM provides convenient non-volatile storage for user-defined functionality. The board also includes the layout for an optional RS-232/422/485 serial port, so that a multi-protocol serial port can be integrated into custom designs.

GPIO-MM contains 8 diagnostic LEDs located in the lower left corner. Off-the-shelf configurations use these LEDs to identify the personality programmed onto the board, while custom designs can use them for any purpose. An additional programmable LED in the lower right corner offers a simple way to verify successful FPGA programming.

Standard feature sets include:

  1. 10 "9513" style 16-bit counter/timers + 8 fixed digital inputs + 8 fixed digital outputs + 48 buffered programmable digital I/O
  2. 48 programmable digital I/O + 48 buffered programmable digital I/O

9513 Counter/Tmers
The GPIO-MM code includes two 9513 counter/timer cores, each containing 5 16-bit counters. This core is based on the popular high performance AMD9513 counter/timer IC. These counters offer extreme flexibility, with programmable input sources, programmable output waveforms, programmable up / down count, one-shot vs. continuous counting, PWM function, and more. Counters can be cascaded together to form 32-bit, 48-bit, etc. wide counters. An input clock of 40MHz provides fine resolution for timing applications.

GPIO-MM Block Diagram

Backward Compatibility
Customers of Diamond's older generation products will appreciate the backward compatibility option of GPIO-MM. The base model GPIO-MM-XT includes all the features of the QMM-5 / QMM-10 board plus the GMM-48 board on one board, with identical register maps. the right side connector duplicates the I/O connector of QMM-10, while the left side connector combines all 48 digital I/O of GMM-48 on a single connector for higher integration and greater compactness. Software applications using previous versions of our Universal Driver software will work on the GPIO-MM-XT without any changes.

Block Diagram

GPIO-MM Block Diagram

I/O Connectors

GPIO-MM Pin Definition

In the standard configurations, the main I/O connectors have the following pinouts. Custom configurations can define any pinout for these connectors. All pinout information is included in the downloadable GPIO-MM Personality Guide.

J3 Counter/Timer I/O (Quartz MM-10 Pin Definition)

In 1 1 2 In 2
Gate 1 3 4 Gate 2
Out 1 5 6 Out 2
In 3 7 8 In 4
Gate 3 9 10 Gate 4
Out 3 11 12 Out 4
In 5 13 14 Out 5
Gate 5 15 16 FOUT
In 6 17 18 In 7
Gate 6 19 20 Gate 7
Out 6 21 22 Out 7
In 8 23 24 In 9
Gate 8 25 26 Gate 9
Out 8 27 28 Out 9
In 10 29 30 Out 10
Gate 10 31 32 Interrupt Input
Dout 7 33 34 Din 7
Dout 6 35 36 Din 6
Dout 5 37 38 Din 5
Dout 4 39 40 Din 4
Dout 3 41 42 Din 3
Dout 2 43 44 Din 2
Dout 1 45 46 Din 1
Dout 0 47 48 Din 0
+5V 49 50 Ground

J4 Digital I/O

Port1 7 1 2 Port4 7
Port1 6 3 4 Port4 6
Port1 5 5 6 Port4 5
Port1 4 7 8 Port4 4
Port1 3 9 10 Port4 3
Port1 2 11 12 Port4 2
Port1 1 13 14 Port4 1
Port1 0 15 16 Port4 0
Port3 7 17 18 Port6 7
Port3 6 19 20 Port6 6
Port3 5 21 22 Port6 5
Port3 4 23 24 Port6 4
Port3 3 25 26 Port6 3
Port3 2 27 28 Port6 2
Port3 1 29 30 Port6 1
Port3 0 31 32 Port6 0
Port2 7 33 34 Port5 7
Port2 6 35 36 Port5 6
Port2 5 37 38 Port5 5
Port2 4 39 40 Port5 4
Port2 3 41 42 Port5 3
Port2 2 43 44 Port5 2
Port2 1 45 46 Port5 1
Port2 0 47 48 Port5 0
+5V 49 50 Ground


Base FPGA Xilinx Spartan II, 200,000 gates, 40K RAM bits
Input clock 40MHz
FPGA code storage Flash memory, field upgradeable via JTAG
ID indicator 8-bit LED display indicates FPGA code personality
No. of I/O pins 100 pins (48 buffered)
Programmable Digital I/O 48 using 8255 cores
Fixed Direction I/O 8 fixed inputs and 8 fixed outputs
Counter/timers 10 16-bit, using 9513 cores
Max counting freq 40MHz
Counter modes Counter, rate/square-wave generator, programmable one-shot,
hardware/software triggered strobe
Output current, buffered I/O Logic 0: 64mA max per line
Ouptut current,
fixed I/O and fixed counter/timers
24mA max
Dimensions 3.55" x 3.775", PC/104 form factor
PC/104 bus 16-bit stackthrough ISA bus
Power supply +5VDC 5%
Operating temperature -40C to +85C standard, all versions
RoHS Compliant

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GPIO-MM Digital I/O Module
available models:
48 Digital I/O plus 10 Counter/Timers PC/104 Module
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Cables and accessories
available models:
50-conductor .1" pitch 18" ribbon cable Data Acquisition
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VDC 2006 Platinum Vendor Award