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| GPIO-MM-12 |
| Reconfigurable 48-line Digital I/O + Counter/Timer PC/104 Module
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48 programmable digital I/O lines based on 8255 cores |
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10 16-bit counter/timers based on 9513 cores with 8 fixed digital inputs and 8 fixed digital outputs |
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On-board EEPROM for user data storage |
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40MHz clock to support high-speed logic and counters |
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3 pin headers for a total of 100 I/O pins |
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Based on a Xilinx Spartan II RAM-based FPGA for field reconfigurability FPGA personality display for easy identification |
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-40°C to +85°C operation |
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PC/104 form factor |
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FREE Universal Driver software included |
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Description |
GPIO-MM-12 is part of a family of reconfigurable digital I/O and counter / timer modules with various port and pin configurations. Each board uses identical hardware with a 200K gate Xilinx Spartan II RAM-based FPGA. The varying configurations are based on different FPGA code. The FPGA code is stored in a flash memory on the board, enabling GPIO-MM-12 to be reprogrammed in the field with different designs, including custom designs.
The GPIO-MM-12 configuration provides 48 digital I/O lines and 10 programmable counter/timers. The counter/timer features are based on our legacy Quartz-MM board, while the 48 digital I/O lines are compatible with our legacy Garnet-MM board. This configuration combines the features of both these boards into one board to reduce your PC/104 stack size and cost.
Other GPIO-MM configurations provide up to 96 digital I/O lines.
Counter/Timer Features
The 10 16-bit counter/timers are provided by two 9513 cores. The high speed
FPGA enables a fast 40MHz clock input, providing greater precision in timing
applications. The counters can be joined under software control to provide 32-bit,
48-bit or 64-bit counters. A variety of input, gate, and output features are
available to implement a wide range of waveform, counting, and timing functions.
The counter / timer I/O connector uses the same pinout as the connector for
Quartz-MM 10-channel boards and includes 16 digital I/O lines configured as
8 inputs and 8 outputs. The fixed I/O and the counter/timer signals feature
ESD-protective circuitry.
Digital I/O Features
The digital I/O includes 48 programmable-direction lines using two 8255 cores. All I/O lines are buffered for enhanced output current. All I/O lines contain jumper-selectable 10Kohm pull-up/pull-down resistors. The 48 I/O lines are contained on a single 50-pin connector, along with system ground and a convenient +5V power pin. The I/O connector presents the digital I/O lines in ABC port order.
ISA Bus Interrupts
GPIO-MM-12 offers two user-programmable interrupt circuits. Possible uses include timer based interrupts or interrupts driven by external signals.
Miscellaneous Features
GPIO-MM-12 includes a 256-byte EEPROM for general-purpose non-volatile storage of user application data. Easy register-level access to the EEPROM simplifies use of this valuable feature.
The board requires only a +5V input and operates from -40°C to +85°C. All board functions are supported by our Universal Driver software for Linux, Windows 2000/XP/CE, DOS, and QNX.
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Block Diagram |
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I/O Headers |
GPIO-MM-12 Pin Definition
J3 Counter/Timer I/O (Quartz MM-10 Pin Definition)
| In 1 |
1 |
2 |
In 2 |
| Gate 1 |
3 |
4 |
Gate 2 |
| Out 1 |
5 |
6 |
Out 2 |
| In 3 |
7 |
8 |
In 4 |
| Gate 3 |
9 |
10 |
Gate 4 |
| Out 3 |
11 |
12 |
Out 4 |
| In 5 |
13 |
14 |
Out 5 |
| Gate 5 |
15 |
16 |
FOUT |
| In 6 |
17 |
18 |
In 7 |
| Gate 6 |
19 |
20 |
Gate 7 |
| Out 6 |
21 |
22 |
Out 7 |
| In 8 |
23 |
24 |
In 9 |
| Gate 8 |
25 |
26 |
Gate 9 |
| Out 8 |
27 |
28 |
Out 9 |
| In 10 |
29 |
30 |
Out 10 |
| Gate 10 |
31 |
32 |
Interrupt Input |
| Dout 7 |
33 |
34 |
Din 7 |
| Dout 6 |
35 |
36 |
Din 6 |
| Dout 5 |
37 |
38 |
Din 5 |
| Dout 4 |
39 |
40 |
Din 4 |
| Dout 3 |
41 |
42 |
Din 3 |
| Dout 2 |
43 |
44 |
Din 2 |
| Dout 1 |
45 |
46 |
Din 1 |
| Dout 0 |
47 |
48 |
Din 0 |
| +5V |
49 |
50 |
Ground |
J4 Digital I/O
| Port1 7 |
1 |
2 |
Port4 7 |
| Port1 6 |
3 |
4 |
Port4 6 |
| Port1 5 |
5 |
6 |
Port4 5 |
| Port1 4 |
7 |
8 |
Port4 4 |
| Port1 3 |
9 |
10 |
Port4 3 |
| Port1 2 |
11 |
12 |
Port4 2 |
| Port1 1 |
13 |
14 |
Port4 1 |
| Port1 0 |
15 |
16 |
Port4 0 |
| Port2 7 |
17 |
18 |
Port5 7 |
| Port2 6 |
19 |
20 |
Port5 6 |
| Port2 5 |
21 |
22 |
Port5 5 |
| Port2 4 |
23 |
24 |
Port5 4 |
| Port2 3 |
25 |
26 |
Port5 3 |
| Port2 2 |
27 |
28 |
Port5 2 |
| Port2 1 |
29 |
30 |
Port5 1 |
| Port2 0 |
31 |
32 |
Port5 0 |
| Port3 7 |
33 |
34 |
Port6 7 |
| Port3 6 |
35 |
36 |
Port6 6 |
| Port3 5 |
37 |
38 |
Port6 5 |
| Port3 4 |
39 |
40 |
Port6 4 |
| Port3 3 |
41 |
42 |
Port6 3 |
| Port3 2 |
43 |
44 |
Port6 2 |
| Port3 1 |
45 |
46 |
Port6 1 |
| Port3 0 |
47 |
48 |
Port6 0 |
| +5V |
49 |
50 |
Ground |
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Specifications |
| Base FPGA |
Xilinx Spartan II, 200,000 gates, 40K RAM bits |
| Input clock |
40MHz |
| FPGA code storage |
Flash memory, field upgradeable via JTAG |
| ID indicator |
8-bit LED display indicates FPGA code personality |
| No. of I/O pins |
100 pins (48 buffered) |
| Programmable Digital I/O |
48 using 8255 cores |
| Fixed Direction I/O |
8 fixed inputs and 8 fixed outputs |
| Counter/timers |
10 16-bit, using 9513 cores |
| Max counting freq |
40MHz |
| Counter modes |
Counter, rate/square-wave generator, pulse-width modulator, programmable one-shot, hardware/software triggered strobe |
| Output current, buffered I/O |
Logic 0: 64mA max per line |
Ouptut current,
fixed I/O and fixed counter/timers |
±24mA max |
| Dimensions |
3.55" x 3.775", PC/104 form factor |
| PC/104 bus |
16-bit stackthrough ISA bus |
| Power supply |
+5VDC ±5% |
| Operating temperature |
-40°C to +85°C standard, all versions |
| RoHS |
Compliant |
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